Name
Abstract | ||
|---|---|---|
The main goal of post-silicon debugging is to locate errors undetected during the pre-silicon verification. Although high speed of hardware prototype can be leveraged to expedite running a large number of realistic test vectors, the low level of observability and controllability of signals inside a prototype is a big concern. Design for Debug (DFD) techniques aim to improve the observability of signals and speed up the root-cause analysis of errors. Incorporation of an Embedded Logic Analyzer (ELA) is introduced as one of the practical DFD techniques. An ELA contains a trigger unit that controls conditions for which trace signals should be captured in a buffer for post-processing. In this paper, we propose a tool to generate hierarchical triggers, providing compact trace information for root-cause analysis. Major advantages of our technique as a means to generate trigger units are: 1) failure localization and root-cause analysis is expedited by keeping the hierarchical trace of interactions leading to failures, 2) overlapped failure patterns can be found by mechanism which results in a 60-65% reduction in hardware overhead compared to the previously proposed method, 3) it can be parameterized to generate several units, making it possible to incorporate checkers into scarce silicon area and enabling on-chip debugging by means of time-multiplexing scheme. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TC.2013.107 | Computers, IEEE Transactions |
Keywords | Field | DocType |
elemental semiconductors,failure analysis,integrated circuit design,integrated circuit reliability,logic analysers,silicon,system-on-chip,trigger circuits,DFD techniques,ELA,Si,SoC design,compact trace information,design for debug techniques,embedded logic analyzer,error location,failure localization,hardware overhead reduction,hierarchical trace,hierarchical trigger generation,on-chip debugging,post-silicon debugging,pre-silicon verification,realistic test vectors,root-cause analysis,scarce silicon area,signal controllability,signal observability,time-multiplexing scheme,trigger generation,Assertion checkers,embedded logic analyzer,hierarchical graph scheme,parallel hierarchical finite state machine,post-silicon debugging,trigger unit | Parameterized complexity,Observability,Controllability,Computer science,Logic analyzer,Parallel computing,Real-time computing,Debugging,Speedup,Embedded system | Journal |
Volume | Issue | ISSN |
63 | 9 | 0018-9340 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. H. Neishaburi | 1 | 79 | 7.51 |
| Zeljko Zilic | 2 | 623 | 71.20 |