M. H. Neishaburi - Citegraph

Author Info

Name	Affiliation	Papers
M. H. NEISHABURI	Department of Electrical Engineering, McGill University, Montreal, Quebec, Canada H3A 2A7	16
Collaborators	Citations	PageRank
23	79	7.51
Referers	Referees	References
130	349	188

Search Limit

100349

Publications (16 rows)

Collaborators (23 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
System on chip failure rate assessment using the executable model of a system	0	0.34	2015
On a New Mechanism of Trigger Generation for Post-Silicon Debugging	0	0.34	2014
NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures	2	0.36	2013
A Fault Tolerant Hierarchical Network on Chip Router Architecture	5	0.45	2013
Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis	4	0.39	2011
Debug Aware AXI-based Network Interface	1	0.37	2011
Enabling efficient post-silicon debug by clustering of hardware-assertions	8	0.49	2010
Reliability aware NoC router architecture using input channel buffer sharing	31	1.01	2009
Graph based test case generation for TLM functional verification	1	0.36	2008
On-Chip Verification of NoCs Using Assertion Processors	2	0.39	2007
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections	10	0.68	2007
Hw/Sw Architecture For Soft-Error Cancellation In Real-Time Operating System	9	0.54	2007
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification	1	0.38	2007
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC	2	0.38	2007
A UML Based System Level Failure Rate Assessment Technique for SoC Designs	3	0.70	2007
System Level Voltage Scheduling Technique Using UML-RT Model	0	0.34	2007

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