Paper Info
Title
Simulation and satisfiability guided counter-example triage for RTL design debugging
Abstract
Regression verification flows in modern integrated circuit development environments expose a plethora of counterexamples during simulation. Sorting these counter-examples today is a tedious and time-consuming process. High level design debugging aims to triage these counter-examples into groups that will be assigned to the appropriate verification and/or design engineers for detailed root cause analysis. In this work, we present an automated triage process that leverages knowledge extracted from simulation and SAT-based debugging. We introduce novel metrics that correlate counter-examples based on the likelihood of sharing the same root cause. Triage is formulated as a pattern recognition problem and solved by hierarchical clustering techniques to generate groups of related counter-examples. Experimental results demonstrate an overall accuracy of 94% for the proposed automated triage framework, which corresponds to a 40% improvement over conventional scripting methods.
Year
DOI
Venue
2014
10.1109/ISQED.2014.6783384
Quality Electronic Design
Keywords
Field
DocType
circuit CAD,computability,computer debugging,high level synthesis,integrated circuit design,pattern clustering,regression analysis,RTL design debugging,SAT-based debugging,automated triage process,hierarchical clustering techniques,high level design debugging,integrated circuit development environments,pattern recognition problem,register transfer level,regression verification,root cause analysis,satisfiability guided counter-example triage,scripting methods
High-level design,Computer science,High-level synthesis,Root cause analysis,Real-time computing,Triage,Register-transfer level,Integrated circuit development,Root cause,Debugging
Conference
ISSN
Citations 
PageRank 
1948-3287
4
0.54
References 
Authors
3
4
Name
Order
Citations
PageRank
Zissis Poulos1669.30
Yu-Shen Yang2928.23
A. Veneris393767.52
Bao Le4244.14