Name
Abstract | ||
|---|---|---|
The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1109/43.3952 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
VLSI,automatic testing,combinatorial circuits,fault location,integrated circuit testing,logic testing,16-valued logic system,GEMINI,VLSI logic circuits,backward implication,delay faults,extended fault model,fault coverage analysis,fault diagnosis,forward propagation,large combinational circuits,logic testing,multiple faults,stuck-at,stuck-open,test generation | Journal | 7 |
Issue | ISSN | Citations |
7 | 0278-0070 | 49 |
PageRank | References | Authors |
3.12 | 7 | 2 |