Name
Abstract | ||
|---|---|---|
The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it could be found that a long path is never activated. This results in more accurate delays. A comparison is made of three arrival time functions, A, B, and R. A is the arrival time as given by exhaustive simulation; B is the arrival time as calculated by a usual block-oriented algorithm; and R is the arrival time, that does functional analysis. It is shown that B contained in R contained in A. The first relation means that R is never more conservative than B and whenever the containment is proper, R is an improvement over B. The second relation means that R is correct in the sense that it will never assert a signal to be valid when it is not valid according to the ideal A. Experimental results showing how often R is an improvement over B are presented. |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1109/12.5996 | Computers, IEEE Transactions |
Keywords | Field | DocType |
logic circuits,logic design,logic testing,arrival time,block-oriented algorithm,functional analysis,logic circuits,timing analysis | Logic synthesis,Logic gate,Digital electronics,Logic testing,Computer science,Parallel computing,Algorithm,Real-time computing,Static timing analysis | Journal |
Volume | Issue | ISSN |
37 | 10 | 0018-9340 |
Citations | PageRank | References |
47 | 17.18 | 3 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Brand | 1 | 292 | 84.65 |
| V. S. Iyengar | 2 | 132 | 25.87 |