Name
Abstract | ||
|---|---|---|
Consideration is given to the use of general-purpose multiprocessors for various simulation tasks. The aims of the work are to define a general framework for the parallel simulation of digital systems and to develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. Specifically, a novel partitioning approach is introduced and used as the basis for the parallel logic and fault simulation of synchronous gate-level designs. Performance experiments with prototype implementations on a message passing and a shared memory machine give promising results, in particular for fault simulation.<> |
Year | DOI | Venue |
|---|---|---|
1989 | 10.1109/ICCAD.1989.77001 | Santa Clara, CA, USA |
Keywords | Field | DocType |
circuit analysis computing,digital simulation,logic CAD,logic testing,parallel processing,cost-performance ratio,fault simulation,general-purpose multiprocessors,message passing,parallel logic simulation,parallel simulation of digital systems,partitioning,shared memory machine,simulation tasks,synchronous gate-level designs | Simulation software,Sequential logic,Logic optimization,Computer science,Parallel computing,Logic simulation,Logic level,Logic family,Register-transfer level,Asynchronous circuit | Conference |
Citations | PageRank | References |
11 | 1.88 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. B. Mueller Thuns | 1 | 88 | 11.23 |
| Saab, D.G. | 2 | 186 | 20.19 |
| Damiano, R.F. | 3 | 11 | 1.88 |
| J. Abraham | 4 | 4905 | 608.16 |