Saab, D.G. - Citegraph

Author Info

Name	Affiliation	Papers
SAAB, D.G.	Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA\|c\|	20
Collaborators	Citations	PageRank
31	186	20.19
Referers	Referees	References
337	407	243

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100407

Publications (20 rows)

Collaborators (31 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling	1	0.38	2011
Exact Path Delay Fault Coverage Calculation of Partitioned Circuits	4	0.47	2009
Hierarchical test generation for systems on a chip	6	0.72	2000
Dynamic fault diagnosis for sequential circuits on reconfigurable hardware	4	0.53	1998
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms	26	1.71	1996
Application of simple genetic algorithms to sequential circuit test generation	32	2.71	1994
Efficient simulation of switch-level circuits in a hierarchical simulation environment	0	0.34	1994
Benchmarking parallel processing platforms: an applications perspective	1	0.38	1993
CHEETA: Composition of hierarchical sequential tests using ATKET	34	2.52	1993
VLSI logic and fault simulation on general-purpose parallel computers	23	1.46	1993
Switch-level timing simulation of bipolar ECL circuits	2	0.40	1993
Fault behavior dictionary for simulation of device-level transients	9	1.73	1993
Hierarchical simulation of MOS circuits using extracted functional models	2	0.54	1992
Site partitioning for distributed redundant disk arrays	0	0.34	1992
Robust switch-level test generation	0	0.34	1992
Fault modeling and testing of self-timed circuits	1	0.41	1991
Beta: behavioral testability analysis	25	1.88	1991
Fault grading of large digital systems	0	0.34	1990
Portable parallel logic and fault simulation	11	1.88	1989
Delay modeling and timing of bipolar digital circuits	5	1.13	1988