Name
Abstract | ||
|---|---|---|
The authors propose a novel test CAD (computer-aided-design) system for ASIC (application-specific integrated circuits), including megacells which automatically insert high-testability logic. The strategy is to access megacells directly and independently. The overhead is only 2% to 3% of the total number of gates. With the proposed system, hierarchically designed logic data can be converted to high-testability logic. It is not necessary for the designers to have specialized knowledge about design-for-testability |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/TEST.1990.114048 | Washington, DC |
Keywords | Field | DocType |
application specific integrated circuits,automatic testing,circuit CAD,logic CAD,ASIC CAD,automatically insert high-testability logic,hierarchical design-for-testability,megacells | Logic synthesis,Testability,Digital electronics,Computer architecture,Logic optimization,Computer science,Electronic engineering,Resistor–transistor logic,Physical design,Register-transfer level,Logic family | Conference |
Citations | PageRank | References |
2 | 0.60 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michiaki Emori | 1 | 44 | 3.53 |
| Takashi Aikyo | 2 | 93 | 11.46 |
| Machida, Yasuhide | 3 | 2 | 0.60 |
| Jun-ichi Shikatani | 4 | 2 | 0.60 |