Name
Abstract | ||
|---|---|---|
The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/ICCD.1990.130180 | ICCD |
Keywords | Field | DocType |
cmos integrated circuits,vlsi,computer vision,neural nets,25-neuron chip,mosis 2-μm cmos technology,vlsi array neuroprocessors,vlsi optical flow computing,adaptive vlsi neuroprocessors,electronic annealing,local connectivity,multilayer stochastic neural network,optical flow,real-time optical flow applications,simulated annealing,stochastic decision rule,supercomputing hardware,velocity-selective hyperneuron chip,very large scale integration,chip,real time,cmos technology,optical computing,neural networks,real time computing,decision rule,stochastic processes,adaptive optics,neural network | Decision rule,Supercomputer,Computer science,Stochastic neural network,CMOS,Real-time computing,Chip,Artificial neural network,Very-large-scale integration,Optical flow | Conference |
Citations | PageRank | References |
1 | 0.35 | 1 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wai-Chi Fang | 1 | 299 | 52.98 |
| B. J. Sheu | 2 | 129 | 28.40 |
| Lee, J.-C. | 3 | 1 | 0.69 |