B. J. Sheu - Citegraph

Author Info

Name	Affiliation	Papers
B. J. SHEU	UNIV SO CALIF,INST INFORMAT SCI,LOS ANGELES,CA 90089	25
Collaborators	Citations	PageRank
42	129	28.40
Referers	Referees	References
302	219	106

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100302

Publications (25 rows)

Collaborators (42 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs?	0	0.34	2015
Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses	0	0.34	2000
A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's	2	0.91	1999
A low power smart vision system based on active pixel sensor integrated with programmable neural processor	0	0.34	1997
A CDMA communication detector with robust near-far resistance using paralleled array processors	1	0.35	1997
Advances in efficient optical links to enhance desktop multimedia processor systems	1	0.36	1997
VLSI design for real-time signal processing based on biologically realistic neural models	2	0.73	1996
A neural network communication equalizer with optimized solution capability	1	0.37	1996
A compact VLSI design for recursive neural networks with hardware annealing capability	0	0.34	1995
An adaptive vector quantizer based on the Gold-Washing method for image compression	11	0.78	1994
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits	2	0.62	1994
Image compression using self-organization networks	24	2.38	1994
Paralleled hardware annealing for optimal solutions on electronic neural networks.	11	1.18	1993
VLSI neuroprocessors for video motion detection.	4	0.69	1993
A programmable analog VLSI neural network processor for communication receivers.	11	1.17	1993
A mixed-signal VLSI neuroprocessor for image restoration	1	0.40	1992
Modified Hopfield neural networks for retrieving the optimal solution.	24	6.11	1991
VLSI image processor using analog programmable synapses and neurons	5	2.33	1990
Automatic layout generation for mixed analog-digital VLSI neural chips	1	0.34	1990
Real-time computing of optical flow using adaptive VLSI neuroprocessors	1	0.35	1990
Parallel digital image restoration using adaptive VLSI neural chips	1	0.34	1990
Temperature dependence modeling for MOS VLSI circuit simulation	2	2.33	1989
An investigation on local minima of a Hopfield network for optimization circuits	4	1.76	1988
An MOS transistor charge model for VLSI design	15	2.32	1988
Inverse-Geometry Dependence of MOS Transistor Electrical Parameters	5	1.24	1987