Name
Abstract | ||
|---|---|---|
A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/ICCD.1991.139992 | Cambridge, MA |
Keywords | Field | DocType |
clocks,delays,logic CAD,pipeline processing,circuit delays,circular pipelines,clock skews,minimum cycle time,multi-phase clocks,single phase clocks,timing model | Pipeline transport,Computer science,Parallel computing,Synchronizing,Real-time computing,Clock skew,Static timing analysis,Clock synchronization | Conference |
ISBN | Citations | PageRank |
0-8186-2270-9 | 5 | 1.29 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Karem A. Sakallah | 1 | 3314 | 287.44 |
| Trevor N. Mudge | 2 | 125 | 92.02 |
| Timothy M. Burks | 3 | 42 | 5.47 |
| Edward S. Davidson | 4 | 922 | 171.30 |