Name
Abstract | ||
|---|---|---|
An analog systolic architecture that uses multiple neuroprocessors for image restoration is presented. For a two-dimensional image, parallel processing is performed for different rows of pixel data and pipelined processing is performed on each row of pixel data. For the image restoration neuroprocessor, local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Interprocessor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to allow multichip operation for high-speed image processing |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/76.157164 | Circuits and Systems for Video Technology, IEEE Transactions |
Keywords | Field | DocType |
VLSI,computerised picture processing,digital signal processing chips,neural nets,pipeline processing,systolic arrays,VLSI neuroprocessor,analog circuitry,analog systolic architecture,high-speed image processing,image restoration,interprocessor communication,local data computation,multiprocessor design,parallel processing,pipelined processing,power dissipation,signal strength,two-dimensional image | Digital signal processing,Computer science,Image processing,Artificial intelligence,Image restoration,Computer hardware,Very-large-scale integration,Computer vision,Parallel computing,Analog image processing,Chip,Pixel,Digital image processing | Journal |
Volume | Issue | ISSN |
2 | 3 | 1051-8215 |
Citations | PageRank | References |
1 | 0.40 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lee, J.-C. | 1 | 1 | 0.40 |
| B. J. Sheu | 2 | 129 | 28.40 |
| Joong-Ho Choi | 3 | 42 | 10.78 |
| Chellappa, R. | 4 | 13050 | 1440.56 |