Name
Abstract | ||
|---|---|---|
An approach, Beta, for computing testability is presented. This approach is based on analyzing the circuit's behavior description data flow graph (DFG). First, each path in the DFG is analyzed to find the set of paths to justify and propagate each data register. Then, register classification follows to diagnose every register's controllability and observability and classify them into several groups. For the most controllable and observable registers, Beta, unlike other testability methods which compute only testability, also tries to derive the exact sequence for justifying and propagating each register. Register classification is also useful in pointing out hard-to-control and hard-to-observe areas of the circuit. This approach has been implemented in a computer program and applied to several examples. These results are verified by a DFG-based test generator and proven to be successful.<> |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/ICCAD.1991.185231 | Santa Clara, CA, USA |
Keywords | Field | DocType |
controllability,logic testing,observability,Beta,behavior description data flow graph,behavioral testability analysis,controllability,observability,register classification | Testability,Exact sequence,Observability,Observable,Controllability,Computer science,Data-flow analysis,Algorithm,Electronic engineering,Testability analysis,Computer program | Conference |
Citations | PageRank | References |
25 | 1.88 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chung-Hsing Chen | 1 | 85 | 6.02 |
| Chienwen Wu | 2 | 55 | 6.46 |
| Saab, D.G. | 3 | 186 | 20.19 |