Name
Abstract | ||
|---|---|---|
Security protocols and encryption algorithms are basically based on random number generators. In this paper, a new random number generator architecture is introduced. The produced number word length is equal to 160 bits. The philosophy architecture relies on the usage of the SHA hash function. The offered security strength of this certain hash function ensures the unpredictability of the produced number. Additionally, an efficient VLSI implementation for FPGA device of the proposed system is described. The proposed architecture is a flexible solution in application cases where the original physical sources of random number generators, such as electrical noise, are not available or at least not convenient. This architecture can also be used in any cryptographic algorithm and encryption/decryption system with high- speed performance. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISCAS.2002.1010592 | Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium |
Keywords | Field | DocType |
VLSI,cryptography,digital arithmetic,field programmable gate arrays,integrated logic circuits,random number generation,160 bit,FPGA device,SHA hash function,VLSI implementation,cryptographic algorithm,encryption algorithms,encryption/decryption system,high-speed performance,produced number word length,random number generator architecture,security protocols,security strength | Cryptographic protocol,Lavarand,Cryptography,Computer science,Encryption,Electronic engineering,Hash function,Random seed,Random number generation,Pseudorandom number generator | Conference |
Volume | Citations | PageRank |
4 | 13 | 3.92 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. Sklavos | 1 | 165 | 23.32 |
| P. Kitsos | 2 | 130 | 15.47 |
| Papadomanolakis, K. | 3 | 13 | 3.92 |
| Odysseas G. Koufopavlou | 4 | 151 | 30.92 |