Name
Abstract | ||
|---|---|---|
In this paper, a VLSI implementation for the SAFER+ encryption algorithm is presented. The combination of security, and high speed implementation, makes SAFER+ a very good choice for wireless systems. The SAFER+ algorithm is a basic component in the authentication Bluetooth mechanism. The relation between the algorithm properties and the VLSI architecture are described. The whole design was captured entirely in VHDL using a bottom-up design and verification methodology. A FPGA device was used for the hardware implementation of the algorithm. The proposed VLSI implementation of the SAFER+ algorithm reduces the covered area about 25 percent, and achieves a data throughput up to 320 Mbit/s at a clock frequency of 20 MHz. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISCAS.2002.1010598 | Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium |
Keywords | Field | DocType |
VLSI,cryptography,digital signal processing chips,field programmable gate arrays,frequency hop communication,high-speed integrated circuits,message authentication,spread spectrum communication,20 MHz,320 Mbit/s,FPGA device,SAFER+ encryption algorithm,VHDL,VLSI implementation,Xilinx VIRTEX XCV400 device,authentication Bluetooth mechanism,bottom-up design methodology,bottom-up verification methodology,high data throughput,high-speed implementation,iterative looping structure,wireless systems | Cryptography,Computer science,Field-programmable gate array,SAFER,Electronic engineering,Encryption,VHDL,Computer hardware,Very-large-scale integration,Clock rate,Bluetooth,Embedded system | Conference |
Volume | Citations | PageRank |
4 | 0 | 0.34 |
References | Authors | |
1 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Kitsos | 1 | 130 | 15.47 |
| Nicolas Sklavos | 2 | 359 | 47.44 |
| Nicolas G. Koufopavlou | 3 | 0 | 0.34 |