Name
Abstract | ||
|---|---|---|
An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/GLSV.1993.224484 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
clocks,flip-flops,logic testing,sequential circuits,Contest sequential test generator,Podem-based test generator,clock partitioning,complexity,flip-flops,path lengths,sequential circuits,test generation,testability | Design for testing,Testability,Sequential logic,Logic testing,Computer science,Test generator,Parallel computing,Electronic engineering,Real-time computing,Partition (number theory) | Conference |
Citations | PageRank | References |
12 | 0.78 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kent L. Einspahr | 1 | 12 | 1.12 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Vishwani D. Agrawal | 3 | 3502 | 470.06 |