Name
Title | ||
|---|---|---|
Memory accesses reordering for interconnect power reduction in sum-of-products computations |
Abstract | ||
|---|---|---|
Techniques for interconnect power consumption reduction in realizations of sum-of-products computations are presented. The proposed techniques reorder the sequence of accesses of the coefficient and data memories to minimize power-costly address and data bus bit switching. The reordering problem is systematically formulated by mapping into the traveling salesman's problem (TSP) for both single and multiple functional unit architectures. The cost function driving the memory accesses reordering procedure explicitly takes into consideration the static information related to algorithms' coefficients and storage addresses and data-related dynamic information. Experimental results from several typical digital signal-processing algorithms prove that the proposed techniques lead to significant bus switching activity savings. The power consumption in the data paths is reduced in most cases as well. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TSP.2002.804060 | Signal Processing, IEEE Transactions |
Keywords | Field | DocType |
digital arithmetic,digital storage,system buses,travelling salesman problems,DSP algorithms,address bit switching,algorithm coefficients,cost function,data bus bit switching,data paths,digital signal processing,interconnect power consumption reduction,memory accesses reordering,sum-of-products computations,traveling salesman's problem | Canonical normal form,Digital signal processor,Computer science,High-level synthesis,Parallel computing,Travelling salesman problem,Interconnection,System bus,Computation,Power consumption | Journal |
Volume | Issue | ISSN |
50 | 11 | 1053-587X |
Citations | PageRank | References |
3 | 0.38 | 16 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. Masselos | 1 | 35 | 7.80 |
| S. Theoharis | 2 | 11 | 2.32 |
| P. Merakos | 3 | 11 | 4.59 |
| T. Stouraitis | 4 | 111 | 13.12 |