Name
Title | ||
|---|---|---|
Efficient simulation of switch-level circuits in a hierarchical simulation environment |
Abstract | ||
|---|---|---|
Switch-level simulation provides a good level of abstraction for simulating digital MOS circuits. For handling large circuits, it is often necessary to represent parts of the circuit by high-level software models, in order to speed up the simulation process. This paper, considers hierarchical switch-level circuits, and investigates the use of extracted functional models at different levels in the hierarchy to increase the efficiency of simulation. A comparative study, on some sample circuits, is used to determine the ideal size of a module that should be simulated using its functional model |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/GLSV.1994.289963 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
MOS integrated circuits,VLSI,digital simulation,integrated logic circuits,logic CAD,CAD,VLSI,digital MOS circuits,extracted functional models,hierarchical simulation environment,high-level software models,ideal size,logic circuits,switch-level circuits | Simulation software,Pass transistor logic,Computer science,Electronic engineering,Logic simulation,Resistor–transistor logic,Logic level,Logic family,Mixed-signal integrated circuit,Integrated injection logic | Conference |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jalal A. Wehbeh | 1 | 12 | 2.68 |
| Saab, D.G. | 2 | 186 | 20.19 |