Name
Abstract | ||
|---|---|---|
We show that a given initialization sequence for a synchronous sequential circuit is not guaranteed to work correctly when arbitrary path delays are present in the circuit. In this paper, we present a novel robust-initialization procedure for sequential circuits. This procedure guarantees the correct initialization of state elements of a sequential circuit regardless of delays in the circuit. Every pattern of the normal initialization sequence is repeatedly clocked in flip-flops, so that excessive delays on combinational paths feeding flip-flops do not prevent the proper initialization. This method guarantees the correct initialization of pipeline circuits. For a general sequential circuit which may have feedbacks, we give a simulation procedure to determine the initial state of the circuit that is guaranteed to be correct for arbitrarily large but bounded delays |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/GLSV.1994.289964 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
circuit analysis computing,flip-flops,logic CAD,logic testing,pipeline processing,sequential circuits,delay independent initialization,feedback,flip-flops,path delays,pipeline circuits,robust-initialization procedure,simulation algorithm,synchronous sequential circuit | Logic synthesis,Logic gate,Sequential logic,Computer science,Parallel computing,Real-time computing,Electronic engineering,Initialization,Electronic circuit,Simulation algorithm,Arbitrarily large,Bounded function | Conference |
Citations | PageRank | References |
2 | 0.51 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tapan J. Chakraborty | 1 | 258 | 26.11 |
| Vishwani D. Agrawal | 2 | 3502 | 470.06 |