Name
Abstract | ||
|---|---|---|
Reports on the successful fabrication of a network chip for large-scale parallel computers. It provides extremely low-latency message delivery in grids of up to 1024 processors or toruses of up to 256 processors. Larger arrays can be constructed using an address embedding technique and the gateway channels supported by the chip. This adds little additional cost in terms of latency. The chip supports, without processor intervention, a number of message consumption modes including point-to-point and broadcast message delivery to the processor. The chip provides deadlock-free, adaptive routing over all shortest paths. It has been fabricated in 1.2 micron CMOS and operates at 25 MHz. We have constructed a 16-node backplane using this chip to demonstrate its operation in a heterogeneous message-passing MIMD computer |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/EMPDP.1993.336369 | Gran Canaria |
Keywords | Field | DocType |
concurrency control,message passing,microprocessor chips,multiprocessor interconnection networks,network routing,parallel machines,1.2 micron,16-node backplane,25 MHz,CMOS,MP1 network chip,address embedding technique,broadcast message delivery,chip fabrication,deadlock-free adaptive routing,gateway channels,heterogeneous message-passing MIMD computer,large-scale parallel computers,low-latency message delivery,message consumption modes,point-to-point message delivery,processor arrays,processor grids,processor toruses,shortest paths | Broadcasting,Backplane,Concurrency control,Computer science,Computer network,Chip,CMOS,Default gateway,Computer hardware,Message passing,MIMD | Conference |
Citations | PageRank | References |
3 | 0.49 | 13 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chris R. Jesshope | 1 | 331 | 42.69 |
| Cruz Izu | 2 | 149 | 23.41 |