Name
Abstract | ||
|---|---|---|
The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.<> |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1109/VTEST.1991.208134 | Atlantic City, NJ, USA |
Keywords | Field | DocType |
application specific integrated circuits,combinatorial circuits,fault location,integrated logic circuits,logic testing,ASIC signal processing designs,DCVSL logic,clock distribution,completion signals,physical faults,scan approach,self-timed circuits,switch-level test generation algorithm | Clock signal,Asynchronous communication,Signal processing,Synchronization,Computer science,Synchronizing,Electronic engineering,Real-time computing,Application-specific integrated circuit,Electronic circuit,Asynchronous circuit | Conference |
Citations | PageRank | References |
1 | 0.41 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stanford S. Guillory | 1 | 1 | 0.41 |
| Saab, D.G. | 2 | 186 | 20.19 |
| A. T. Yang | 3 | 145 | 35.28 |