Name
Abstract | ||
|---|---|---|
In this paper we deal with polynomial evaluation based on new processor architectures for multimedia applications. We introduce some algorithms to take advantage of the new attributes of multimedia processors, such as VLIW (very long instruction word) and SIMD (single instruction multiple data architecture) architectures. Algorithms to support polynomial evaluation based only in addition/shift operations and other different algorithms with MAC (multiply-and-add) instructions are analyzed and tailored to subword parallelism units of the new processors. Both potential instruction-level and machine-level parallelism are fully exploited through concurrent use of all functional units. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ASAP.2002.1030725 | ASAP |
Keywords | Field | DocType |
digital signal processing chips,instruction sets,microprocessor chips,multimedia computing,parallel algorithms,parallel architectures,polynomials,MAC instructions,SIMD,VLIW,addition/shift operations,digital signal processing,functional unit concurrent use,instruction-level parallelism,machine-level parallelism,multimedia extensions,multimedia processor polynomial evaluation algorithms,multiply-and-add instructions,processor architecture,single instruction multiple data architecture,subword parallelism units,very long instruction word architecture | Instruction-level parallelism,Computer architecture,Digital signal processing,Polynomial,Very long instruction word,Instruction set,Computer science,Parallel algorithm,Parallel computing,SIMD,Multimedia,Microarchitecture | Conference |
ISSN | ISBN | Citations |
2160-0511 | 0-7695-1712-9 | 6 |
PageRank | References | Authors |
0.62 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Julio Villalba | 1 | 219 | 23.56 |
| Bandera, G. | 2 | 6 | 0.62 |
| Gonzalez, M.A. | 3 | 6 | 0.62 |
| Javier Hormigo | 4 | 113 | 19.45 |