Name
Abstract | ||
|---|---|---|
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a code transformation targeted to reduce capacity misses. This paper presents a novel systematic approach to perform near-optimal loop tiling based on an accurate data locality analysis (cache miss equations) and a powerful technique to search the solution space that is based on a genetic algorithm. The results show that this approach can remove practically all capacity misses for all considered benchmarks. The reduction of replacement misses results in a decrease of the miss ratio that can be as significant as a factor of 7 for the matrix multiply kernel. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ICPPW.2002.1039779 | ICPP Workshops |
Keywords | DocType | ISSN |
cache storage,genetic algorithms,performance evaluation,storage management,cache miss equations,genetic algorithm,loop tiling,memory hierarchy,memory locality analysis,performance evaluation,program transformations | Conference | 1530-2016 |
ISBN | Citations | PageRank |
0-7695-1680-7 | 16 | 0.99 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaume Abella | 1 | 1046 | 76.34 |
| Antonio González | 2 | 3178 | 229.66 |
| Josep Llosa | 3 | 574 | 39.30 |
| Xavier Vera | 4 | 59 | 4.50 |