Name
Title | ||
|---|---|---|
IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips |
Abstract | ||
|---|---|---|
To enable the efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be re-used in one, well-defined debug architectures at chip-level. This paper describes a chip-level architecture for controlling multiple IEEE 1149.1 compliant debug interfaces on a single system chip. The presented architecture is not only fully compliant with IEEE 1149.1 with regard to the chip-level debug and boundary scan hardware, but also as to whether or not the bypass multiplexer is activated. Chip-level TAP support is also presented to allow multiple debugger tools to control debug operations in multiple heterogeneous cores via this architecture. As an experiment, the proposed architecture is mapped on an FPGA to verify concurrent debug of multiple cores. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TEST.2002.1041745 | ITC '02 Proceedings of the 2002 IEEE International Test Conference |
Keywords | Field | DocType |
IEEE standards,VLSI,automatic testing,boundary scan testing,digital integrated circuits,integrated circuit testing,logic testing,system-on-chip,IEEE 1149.1 compliant debug interfaces,IEEE 1149.1-compliant access architecture,boundary scan hardware,bypass multiplexer activation,chip-level TAP support,chip-level architecture,core-based system chip,debug functionality,digital system chips,multiple core debug,multiple heterogeneous cores | Boundary scan,x86 debug register,System on a chip,Debug menu,Debugger,Computer science,Background debug mode interface,Chip,Real-time computing,Debugging,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-7542-4 | 18 |
PageRank | References | Authors |
2.16 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bart Vermeulen | 1 | 142 | 13.81 |
| Tom Waayers | 2 | 128 | 11.47 |
| Sjaak Bakker | 3 | 19 | 2.69 |