Name
Abstract | ||
|---|---|---|
Metal oxide semiconductor (MOS) technology is highly popular currently due to the many advantages that it provides. It has been shown that conventional methods of testing are not applicable to MOS circuits. A switch-level model is used to generate a sequence of test vectors for a variety of MOS circuits, including those containing pass transistor logic.<> |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/VTEST.1992.232733 | Atlantic City, NJ, USA |
Keywords | Field | DocType |
MOS integrated circuits,integrated circuit testing,integrated logic circuits,logic testing,MOS circuits,pass transistor logic,robust test generation,switch-level model,test vectors | Logic gate,Pass transistor logic,Computer science,Logic testing,Electronic engineering,Robustness (computer science),Electronic circuit,Electrical engineering,Feedback circuits,Semiconductor | Conference |
ISBN | Citations | PageRank |
0-7803-0623-6 | 0 | 0.34 |
References | Authors | |
7 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mathew, B. | 1 | 0 | 0.34 |
| Saab, D.G. | 2 | 186 | 20.19 |