Name
Abstract | ||
|---|---|---|
A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/43.238606 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
clocks,pipeline processing,synchronisation,clock schedule,coincident multiphase clocks,concurrency,label-sensitive latches,latch-controlled pipelined circuits,long-path delays,lower bound,minimum cycle time,multiphase synchronous clocking,optimum cycle time,single-phase clocking,synchronous operation,timing constraints,timing model,wave pipelining | Journal | 12 |
Issue | ISSN | Citations |
8 | 0278-0070 | 13 |
PageRank | References | Authors |
1.27 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Karem A. Sakallah | 1 | 3314 | 287.44 |
| Trevor N. Mudge | 2 | 125 | 92.02 |
| Burks, T.M. | 3 | 13 | 1.27 |
| Edward S. Davidson | 4 | 922 | 171.30 |