Name
Abstract | ||
|---|---|---|
We introduce a new gate sizing rule for significantly improving the speed performance of static logic paths designed in submicron CMOS technology. This methodology is based on the definition of local gate sizing criterion. It is directly deduced from analytical models of the output transition time and of the short circuit power dissipation, which are validated on a 0.18 μm CMOS process. This sizing methodology is shown to offer a low power implementation alternative that can be used as an initial solution, prior to any logic path optimization. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/APCCAS.2002.1115250 | Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference |
Keywords | Field | DocType |
CMOS logic circuits,logic design,logic gates,low-power electronics,0.18 micron,gate sizing rule,gate speed improvement,gate speed performance,local gate sizing criterion,low power implementation,minimal power dissipation,output transition time,short circuit power dissipation,sizing methodology,static logic paths,submicron CMOS technology | Inverter,Logic gate,Pass transistor logic,Control theory,Computer science,CMOS,NAND gate,Adiabatic circuit,Electronic engineering,Logic family,Gate equivalent | Conference |
Volume | ISBN | Citations |
2 | 0-7803-7690-0 | 0 |
PageRank | References | Authors |
0.34 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Philippe Maurine | 1 | 0 | 0.34 |
| Xavier Michel | 2 | 0 | 0.34 |
| Nadine Azémard | 3 | 0 | 0.68 |
| Daniel Auvergne | 4 | 145 | 31.67 |