| Low Power Oriented CMOS Circuit Optimization Protocol | 2 | 0.44 | 2005 |
| Technical Program Committee | 0 | 0.34 | 2004 |
| Design Techniques for EEPROMs Embedded in Portable Systems on Chips | 5 | 0.67 | 2003 |
| Crosstalk Measurement Technique for CMOS ICs | 0 | 0.34 | 2002 |
| Structure Independent Representation of Output Transition Time for CMOS Library | 1 | 0.38 | 2002 |
| Gate speed improvement at minimal power dissipation | 0 | 0.34 | 2002 |
| Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications | 0 | 0.34 | 2002 |
| Transistor Level Synthesis Dedicated to Fast I.P. Prototyping | 0 | 0.34 | 2002 |
| Transition time modeling in deep submicron CMOS | 27 | 2.42 | 2002 |
| POPS: A tool for delay/power performance optimization | 6 | 0.51 | 2001 |
| Delay bound determination for timing closure satisfaction | 0 | 0.34 | 2001 |
| Output transition time modeling of CMOS structures | 8 | 0.95 | 2001 |
| Feasible Delay Bound Definition | 0 | 0.34 | 2001 |
| Gate Sizing for Low Power Design | 0 | 0.34 | 2001 |
| Second Generation Delay Model for Submicron CMOS Process | 0 | 0.34 | 2000 |
| Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions | 1 | 0.53 | 2000 |
| Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design | 2 | 0.48 | 2000 |
| Delay-power performance analysis | 0 | 0.34 | 1999 |
| RF Interface Design Using Mixed-Mode Methodology | 0 | 0.34 | 1999 |
| A Virtual CMOS Library Approach for East Layout Synthesis | 3 | 0.66 | 1999 |
| A novel macromodel for power estimation in CMOS structures | 19 | 1.78 | 1998 |
| Temperature effect on delay for low voltage applications | 18 | 4.55 | 1998 |
| Delay propagation effect in transistor gates | 2 | 0.78 | 1996 |
| Design and selection of buffers for minimum power-delay product | 12 | 1.91 | 1996 |
| Explicit evaluation of short circuit power dissipation for CMOS logic structures | 11 | 2.58 | 1995 |
| Delay modelling improvement for low voltage applications | 2 | 3.11 | 1995 |
| Influence of Locig Block Layout Architecture on FPGA Performance | 1 | 0.37 | 1994 |
| Post-layout timing simulation of CMOS circuits | 3 | 0.60 | 1993 |
| P.SIZE: a sizing aid for optimized designs | 1 | 0.67 | 1992 |
| TVA: A timing verifier with analytic temporal modelling | 0 | 0.34 | 1991 |
| Formal sizing rules of CMOS circuits | 7 | 0.99 | 1991 |
| Path Runner: an accurate and fast timing analyser | 2 | 0.69 | 1990 |
| FSPICE: a tool for fault modelling in MOS circuits | 12 | 2.55 | 1985 |
