Paper Info
Title
General framework for removal of clock network pessimism
Abstract
The paper presents a simple yet powerful general theoretical framework and efficient implementation for removal of clock network timing pessimism. We address pessimism in static timing analysis (STA) tools caused by considering delay variation along common segments of clock paths. The STA tools compute setup (hold) timing slack based on conservative combinations of late (early) launching and early (late) capturing arrival times. To avoid exponential-time path-based analysis the STA tools use both early and late arrival times on gates common to both launching and capturing paths. It is impossible in real circuit and is observed as the clock network pessimism in STA. Our approach supports any kind of delay variation though the typical causes of the pessimism are process, voltage, and temperature on-chip variation, and reconvergence in clock network. We propose a new theoretical framework that allows to apply known graph algorithms instead of time consuming forward and backward multi-pass tracing algorithms and heuristics that are limited to some network topologies [4]. The new graph-based framework supports clock networks of virtually any size and type, e.g., tree, mesh, hybrid, clock gating, chains of multipliers and dividers, loops in such chains, etc. The implementation based on the proposed framework has proven its strength in a commercial sign-off static timing analyzer and thus is helping hundreds of designers to achieve faster clock speeds of their chips.
Year
DOI
Venue
2002
10.1109/ICCAD.2002.1167599
ICCAD
Keywords
Field
DocType
circuit analysis computing,delay estimation,digital integrated circuits,graph theory,timing circuits,clock network timing pessimism removal,delay variation,design verification,general theoretical framework,graph algorithms,graph-based framework,setup timing slack,static timing analysis tools
Vector clock,Timing failure,Clock gating,Clock network,Clock drift,Computer science,Real-time computing,Network topology,Electronic engineering,Static timing analysis,Digital clock manager
Conference
ISSN
ISBN
Citations 
1092-3152
0-7803-7607-2
13
PageRank 
References 
Authors
1.65
4
2
Name
Order
Citations
PageRank
Jindrich Zejda1131.65
Paul Frain2131.65