A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation | 0 | 0.34 | 2022 |
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay | 0 | 0.34 | 2022 |
A 24gb/S/Pin 8gb Gddr6 With A Half-Rate Daisy-Chain-Based Clocking Architecture And Io Circuitry For Low-Noise Operation | 0 | 0.34 | 2021 |
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. | 0 | 0.34 | 2020 |
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications | 4 | 0.53 | 2015 |
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques | 6 | 0.94 | 2015 |