Name
Abstract | ||
|---|---|---|
In this paper, we present a new LFSR reseeding scheme for scan-based BIST, suitable for circuits with random-pattern-resistant faults. The proposed scheme eliminates the need of a ROM for storing the seeds since the reseedings are performed dynamically by inverting some selected bits of the LFSR register. A time-to-market efficient algorithm is also presented for selecting the reseeding points in the test sequence, as well as a proper seed at each point. This algorithm targets complete fault coverage and minimization of the resulting test length and hardware overhead. Experimental results on ISCAS '85 and ISCAS '89 benchmark circuits demonstrate the advantages of this new LFSR reseeding approach in terms of area overhead and test application time. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ATS.2002.1181712 | Test Symposium, 2002. |
Keywords | Field | DocType |
boundary scan testing,built-in self test,integrated circuit design,integrated circuit modelling,integrated circuit testing,logic design,logic testing,shift registers,LFSR register bit inversion,ROM-less LFSR reseeding schemes,built-in self-test,dynamic reseeding,fault coverage,hardware area overhead,linear feedback shift registers,random-pattern-resistant faults,reseeding point selection algorithms,scan-based BIST,test application time,test length minimization,test sequence reseeding points | Logic synthesis,Shift register,Linear feedback shift register,Fault coverage,Computer science,Real-time computing,Electronic engineering,Minification,Integrated circuit design,Electronic circuit,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1081-7735 | 0-7695-1825-7 | 6 |
PageRank | References | Authors |
0.48 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. Kalligeros | 1 | 113 | 6.90 |
| X. Kavousianos | 2 | 161 | 12.90 |
| D. Nikolos | 3 | 291 | 31.38 |