Name
Abstract | ||
|---|---|---|
Genetic Algorithms have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of a previously proposed the GA-based ATPG algorithm: in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved Fault Coverage and required CPU time. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EDTC.1996.494328 | ED&TC |
Field | DocType | ISSN |
Stuck-at fault,Automatic test pattern generation,Sequential logic,Fault coverage,CPU time,Logic testing,Computer science,Algorithm,Real-time computing,Electronic engineering,Minification,Genetic algorithm | Conference | 1066-1409 |
ISBN | Citations | PageRank |
0-8186-7423-7 | 30 | 1.43 |
References | Authors | |
6 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Corno | 1 | 602 | 55.65 |
| P. Prinetto | 2 | 516 | 55.23 |
| Maurizio Rebaudengo | 3 | 746 | 79.10 |
| Matteo Sonza Reorda | 4 | 1250 | 136.66 |
| R. Mosca | 5 | 30 | 1.43 |