Name
Title | ||
|---|---|---|
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms |
Abstract | ||
|---|---|---|
This paper discusses a new approach for generating test vectors, using test cultivation, for both combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The hierarchical technique used in the analysis drastically reduces the memory requirements, allowing test generation for large circuits. The test cultivation algorithms are simulation-based and a test set can be cultivated for any circuit that can be simulated logically. In particular, general MOS digital designs can be handled, and both stuck-at and transistor faults can be accurately modeled. Using the approach, tests were generated with very high fault coverage for gate-level circuits as well as for transistor level circuits |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/43.541447 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
MOS logic circuits,VLSI,automatic testing,genetic algorithms,integrated circuit testing,logic testing,sequential circuits,MOS digital design,VLSI,automatic test vector cultivation,combinational circuit,gate-level circuit,genetic algorithm,hierarchical technique,logic simulation,sequential circuit,stuck-at faults,transistor faults,transistor level circuit | Journal | 15 |
Issue | ISSN | Citations |
10 | 0278-0070 | 26 |
PageRank | References | Authors |
1.71 | 21 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Saab, D.G. | 1 | 186 | 20.19 |
| Saab, Y.G. | 2 | 26 | 1.71 |
| J. Abraham | 3 | 4905 | 608.16 |