Name
Abstract | ||
|---|---|---|
This paper presents our experience on domain-specific high-level modeling and synthesis for Fujitsu ATM switch design. We propose a high-level design methodology using VHDL, where ATM switch architectural features are considered during behavior modeling, and a high-level synthesis compiler, MEBS, is prototyped to synthesize the behavior model down to a gate-level implementation. Since the specific ATM switch architecture is incorporated into both modeling and syntheses phases, a high-quality design is efficiently derived. The synthesis results show that given the design constraints, the proposed high-level design methodology can produce a gate-level implementation by MEBS with about 15% area reduction in shorter design cycle when compared with manual design |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/DAC.1996.545643 | Las Vegas, NV |
Keywords | Field | DocType |
asynchronous transfer mode,hardware description languages,high level synthesis,logic CAD,ATM switch design,MEBS,VHDL,architectural features,behavior modeling,domain-specific high-level modeling,gate-level implementation,high-level design methodology,high-level synthesis,high-level synthesis compiler,high-quality design | Permission,Computer architecture,Computer science,High-level synthesis,Design methods,Asynchronous Transfer Mode,Real-time computing,Compiler,Electronic design automation,VHDL,Embedded system,Hardware description language | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-7803-3294-6 | 6 |
PageRank | References | Authors |
0.65 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mike Tien-Chien Lee | 1 | 443 | 71.04 |
| Yu-Chin Hsu | 2 | 538 | 60.30 |
| Ben Chen | 3 | 6 | 0.65 |
| Masahiro Fujita | 4 | 6 | 0.65 |