Paper Info
Title
Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects
Abstract
The actual operation of a complementary metal-oxide-semiconductor (CMOS) gate driving long resistance inductance-capacitance (RLC) interconnects is investigated in this paper. Using the alpha-law model, inductance effects of long on-chip interconnects on the operating region of submicron CMOS line-driver transistors are analysed. The study demonstrates that both the linear and the saturation modes of operation may be equally present during buffer switching and thus neither saturation region nor linear region model can be used solely to characterise the operation of the transistors. A computationally efficient closed form expression for the portion of the switching time the MOS transistors of a line driver actually operate in the saturation region is also presented. Proposed formulae, particularly suitable for CAD tools implementation, is characterised by a 15% accuracy as compared to SPICE simulations for a wide range of line parameters.
Year
DOI
Venue
2003
10.1109/ICECS.2003.1301829
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference
Keywords
DocType
Volume
CMOS digital integrated circuits,SPICE,buffer circuits,circuit CAD,circuit simulation,driver circuits,integrated circuit design,integrated circuit interconnections,CAD tools implementation,CMOS line-driver transistors,SPICE simulations,alpha-law model,buffer switching,closed form expression,deep-submicron CMOS buffers,inductive interconnects,linear modes,long on-chip interconnects,operating mode analysis,output response,saturation modes
Conference
2
ISBN
Citations 
PageRank 
0-7803-8163-7
0
0.34
References 
Authors
2
1
Name
Order
Citations
PageRank
Gregorio Cappuccino13610.11