Name
Abstract | ||
|---|---|---|
In modern security, the need for safe cryptographic algorithms that are hardware implemental is great. A hardware architecture is proposed in this paper, for the implementation of the ICE encryption algorithm. Since this cipher is optimized for use on software, a hardware implementation of that algorithm that achieves good performance results has much interest. The proposed implementation can be used for both encryption and decryption processes. It is a folded architecture using feedback logic, designed for small chip covered area and high speed performance. The proposed architecture was implemented by using an FPGA device. The achieved throughput is equal to 116 Mbit/sec, using a system clock with frequency up to 29.1 MHz. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICECS.2003.1301983 | Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference |
Keywords | DocType | Volume |
VLSI,circuit feedback,clocks,cryptography,field programmable gate arrays,high-speed integrated circuits,integrated circuit design,logic design,telecommunication security,116 Mbit/s,29.1 MHz,FPGA device,FPGA implementation,ICE encryption algorithm,VLSI architecture,chip covered area,decryption process,encryption process,feedback logic,folded architecture,hardware architecture,hardware implemental safe cryptographic algorithms,hardware implementation performance,high speed performance,security,software optimized cipher,system clock frequency,throughput | Conference | 1 |
ISBN | Citations | PageRank |
0-7803-8163-7 | 2 | 0.44 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fournaris, A.P. | 1 | 38 | 2.92 |
| N. Sklavos | 2 | 165 | 23.32 |
| O. Koufopavlou | 3 | 256 | 28.43 |