| Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers | 0 | 0.34 | 2020 |
| VLSI Design and Implementation of Homophonic Security System | 1 | 0.43 | 2012 |
| VITAL++, a new communication paradigm: embedding P2P technology in next generation networks | 28 | 1.15 | 2011 |
| Full custom low-power/high performance DDP-based Cobra-H64 cipher | 0 | 0.34 | 2010 |
| Versatile multiplier architectures in GF(2k) fields using the Montgomery multiplication algorithm | 6 | 0.47 | 2008 |
| Towards a service-enabled distributed router architecture | 1 | 0.36 | 2008 |
| Applying systolic multiplication-inversion architectures based on modified extended Euclidean algorithm for GF(2k) in elliptic curve cryptography | 3 | 0.47 | 2007 |
| An optimal low-power/high performance DDP-based Cobra-H64 cipher | 0 | 0.34 | 2007 |
| Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security | 3 | 0.84 | 2006 |
| Applying Low Power Techniques in AES MixColumn/InvMixColumn Transformations | 2 | 0.43 | 2006 |
| High speed networking security: design and implementation of two new DDP-based ciphers | 23 | 1.30 | 2005 |
| Cryptography: circuits and systems approach | 3 | 0.48 | 2005 |
| Implementation of the SHA-2 Hash Family Standard Using FPGAs | 41 | 4.50 | 2005 |
| On the hardware implementation of RIPEMD processor: Networking high speed hashing, up to 2Gbps | 2 | 0.41 | 2005 |
| New class of the FPGA efficient cryptographic primitives | 0 | 0.34 | 2004 |
| Computer Network Security: Report from MMM-ACNS | 5 | 0.67 | 2004 |
| 64-bit Block ciphers: hardware implementations and comparison analysis | 9 | 0.68 | 2004 |
| Efficient architecture and hardware implementation of the Whirlpool hash function | 10 | 0.96 | 2004 |
| Area optimized architecture and VLSI implementation of RC5 encryption algorithm | 4 | 0.55 | 2003 |
| VLSI architecture and FPGA implementation of ICE encryption algorithm | 2 | 0.44 | 2003 |
| A policy-based management architecture for active and programmable networks | 14 | 0.82 | 2003 |
| VLSI IMPLEMENTATION OF THE KEYED-HASH MESSAGE AUTHENTICATION CODE FOR THE WIRELESS APPLICATION PROTOCOL | 8 | 0.88 | 2003 |
| VLSI implementations of the triple-DES block cipher. | 2 | 0.46 | 2003 |
| An efficient reconfigurable multiplier architecture for Galois field GF(2m) | 34 | 1.78 | 2003 |
| Data dependent rotations, a trustworthy approach for future encryption systems/ciphers: low cost and high performance | 2 | 0.43 | 2003 |
| Architectures and VLSI implementations of the AES-Proposal Rijndael | 34 | 3.76 | 2002 |
| Power exploration of multimedia applications realized on embedded cores | 4 | 0.50 | 1999 |
| Switching response modeling of the CMOS inverter for sub-micron devices | 2 | 0.47 | 1998 |
| Data link control emulation: rapid prototyping for high-speed networks | 1 | 0.39 | 1998 |
| Analytical Model for the CMOS Short-Circuit Power Dissipation | 1 | 0.45 | 1998 |
| Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices | 3 | 0.54 | 1996 |
| Space-Time Representation of Iterative Algorithms and the Design of Regular Processor Arrays | 1 | 0.36 | 1993 |
| Image reconstruction on a special purpose array processor | 0 | 0.34 | 1992 |
| Analysis of TCP/IP for high performance parallel implementations | 7 | 1.07 | 1992 |
| Array processor for LS FIR system identification | 0 | 0.34 | 1991 |
| A generator for a number format conversion IC | 0 | 0.34 | 1990 |
