Name
Abstract | ||
|---|---|---|
In this paper we address the problem of delay constraint distribution on CMOS combinatorial paths. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on Newton-Raphson like algorithms. Validation is obtained on a 0.25 μm process by comparing the different constraint distribution techniques on various benchmarks. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329494 | Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium |
Keywords | Field | DocType |
CMOS logic circuits,Newton-Raphson method,combinational circuits,integrated circuit modelling,logic design,0.25 micron,CMOS combinatorial paths,CMOS gate sizing technique,Newton-Raphson like algorithms,delay bound,delay constraint distribution | Delay calculation,Logic synthesis,Space technology,Computer science,Electronic engineering,Combinational logic,CMOS,Linear programming,Dimensioning,Newton's method | Conference |
Volume | ISBN | Citations |
5 | 0-7803-8251-X | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Verle, A. | 1 | 0 | 0.34 |
| Xavier Michel | 2 | 9 | 1.27 |
| P. Maurine | 3 | 142 | 14.46 |
| N. Azemard | 4 | 104 | 14.17 |