N. Azemard - Citegraph

Author Info

Name	Affiliation	Papers
N. AZEMARD	(Correspd. E-mail: nadine.azemard@lirmm.fr) LIRMM, UMR CNRS/Université de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France	16
Collaborators	Citations	PageRank
27	104	14.17
Referers	Referees	References
212	205	115

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100212

Publications (16 rows)

Collaborators (27 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization	7	0.51	2011
Timing margin evaluation with a simple statistical timing analysis flow	0	0.34	2009
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier	0	0.34	2008
A simple statistical timing analysis flow and its application to timing margin evaluation	4	0.49	2007
Temperature and voltage aware timing analysis: application to voltage drops	3	0.42	2007
Temperature- and Voltage-Aware Timing Analysis	23	1.52	2007
Timing analysis in presence of supply voltage and temperature variations	5	0.43	2006
Statistical characterization of library timing performance	2	0.44	2006
Low Power Oriented CMOS Circuit Optimization Protocol	2	0.44	2005
Circuit optimization based on speed indicators.	0	0.34	2005
Delay bound based CMOS gate sizing technique	0	0.34	2004
Transition time modeling in deep submicron CMOS	27	2.42	2002
Design and selection of buffers for minimum power-delay product	12	1.91	1996
Explicit evaluation of short circuit power dissipation for CMOS logic structures	11	2.58	1995
P.SIZE: a sizing aid for optimized designs	1	0.67	1992
Formal sizing rules of CMOS circuits	7	0.99	1991

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