Title
New static compaction techniques of test sequences for sequential circuits
Abstract
This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others eliminated. The problem is NP-complete, and we adopt Genetic Algorithms to obtain optimal solutions with acceptable computational requirements. As it requires just one preliminary Fault Simulation experiment, the approach is much more efficient than others proposed before; experimental results gathered with Test Sets generated by different ATPG tools show that the method is able to reduce the size of the Test Set by a factor varying between 50% and 62%.
Year
DOI
Venue
1997
10.1109/EDTC.1997.582327
Paris
Keywords
Field
DocType
automatic testing,genetic algorithms,logic testing,sequential circuits,ATPG tool,NP-complete problem,fault detection,fault simulation,genetic algorithm,sequential circuit,static compaction,test sequence
Automatic test pattern generation,Sequential logic,Fault detection and isolation,Computer science,Test sequence,Algorithm,Automatic testing,Real-time computing,Compaction,Genetic algorithm,Test set
Conference
ISSN
ISBN
Citations 
1066-1409
0-8186-7786-4
35
PageRank 
References 
Authors
1.56
6
4
Name
Order
Citations
PageRank
F. Corno160255.65
P. Prinetto251655.23
M. Rebaudengo359345.50
Sonza Reorda, M.41389.52