Name
Abstract | ||
|---|---|---|
Recently, manufacturing defects including opens in the interconnect layers have been increasing. Therefore, a failure analysis for open faults has become important in manufacturing. Moreover, the failure analysis for open faults under BIST environment is demanded. Since the quality of the failure analysis is engaged by the resolution of locating the fault, we propose the method for locating single open fault at a stem, based on only detecting/un-detecting information on tests. Our method deduces candidate faulty stems based on the number of detections for single stuck-at fault at each of fanout branches, by performing single stuck-at fault simulation with both detecting and un-detecting tests. To improve the ability of locating the fault, the method reduces the candidate faulty stems based on the number of detections for multiple stuck-at faults at fanout branches of the candidate faulty stem, by performing multiple stuck-at fault simulation with detecting tests. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ATS.2004.44 | Asian Test Symposium |
Keywords | Field | DocType |
VLSI,automatic test pattern generation,built-in self test,circuit analysis computing,combinational circuits,failure analysis,fault location,integrated circuit testing,BIST,failure analysis,fault location,interconnect layers,manufacturing defects,open faults,stuck-at fault | Stuck-at fault,Automatic test pattern generation,Fault coverage,Computer science,Software fault tolerance,Real-time computing,Electronic engineering,Fault (power engineering),Fault model,Reliability engineering,Built-in self-test,Fault indicator | Conference |
ISSN | ISBN | Citations |
1081-7735 | 0-7695-2235-1 | 3 |
PageRank | References | Authors |
0.43 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Y Sato | 1 | 678 | 53.94 |
| Hiroshi Takahashi | 2 | 148 | 24.32 |
| Yoshinobu Higami | 3 | 140 | 27.24 |
| Yuzo Takamatsu | 4 | 150 | 27.40 |