Name
Abstract | ||
|---|---|---|
In present day VLSI ICs, intra-die processing variations are becoming harder to control, resulting in a large skew in the clock signals at the end of the clock distribution network. We describe a buffered H-tree technique to distribute the clock signal and to de-skew a clock network. The clock shielding wires (which are connected to GND in normal operation) are, in de-skewing mode, used to selectively return the clock signal for de-skewing, and for serial communication with the clock distribution sites for skew adjustment. Our forward and return clock networks are buffered, with identically sized and co-located wires and buffers. This results in both these networks exhibiting identical delay characteristics in the presence of intra-die process variations. Unlike existing approaches, our method utilizes a single phase detection circuit, and can achieve a very low maximum chip-level clock skew. This skew value is not dependent on the resolution of the phase detector. Further, our technique can be applied dynamically, either at boot time or periodically during the operation of the IC, as necessary. Additionally, our buffered H-tree enables us to implement efficient clock gating by allowing the user to turn off clocks in the distribution network itself, thus disabling entire sections of the clock network. We demonstrate the utility of our technique on a 6-level H-tree clock distribution network. In a clock distribution network which is initially skewed by up to 300ps, our technique can de-skew signals to within 4ps of each other. We show that the total wiring area of our clock distribution and de-skewing methodology is about 35% higher than a traditional H-tree (which does not have a deskewing functionality), while the active logic area overhead is about 25%. The power consumption of our network is 5% lower than that of a traditional H-tree network with no de-skewing functionality. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICCAD.2004.1382651 | ICCAD |
Keywords | Field | DocType |
VLSI,circuit optimisation,clocks,integrated circuit design,logic design,phase detectors,VLSI integrated circuit,buffered H-tree technique,chip-level clock skew,clock distribution network,clock distribution sites,clock gating,clock shielding wires,clock signals,de-skewing mode,delay characteristics,dynamic de-skewing methodology,intra-die processing variations,phase detector,serial communication,single phase detection circuit,skew adjustment | Clock gating,Clock network,Clock drift,Computer science,Clock domain crossing,Electronic engineering,Clock skew,Digital clock manager,Clock angle problem,CPU multiplier | Conference |
ISSN | ISBN | Citations |
1092-3152 | 0-7803-8702-3 | 27 |
PageRank | References | Authors |
1.42 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kapoor, A. | 1 | 27 | 1.42 |
| Nikhil Jayakumar | 2 | 215 | 20.42 |
| Sunil P. Khatri | 3 | 1213 | 137.09 |