Name
Title | ||
|---|---|---|
Speeding up program execution using reconfigurable hardware and a hardware function library |
Abstract | ||
|---|---|---|
This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a uniprocessor host and a board with dynamically reconfigurable FPGAs and memory modules; second, a library of functions pre-synthesized for hardware or software implementation; and third, a tool which takes as input an application described in C and partitions it into hardware and software parts at functional granularity using information obtained by profiling the application. An important feature of the partitioning tool is a new efficient heuristic specifically suited for the architecture with reconfigurable hardware |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICVD.1998.646641 | VLSI Design |
Keywords | Field | DocType |
field programmable gate arrays,high level synthesis,reconfigurable architectures,co-design environment,compute intensive applications,dynamically reconfigurable FPGA board,functional granularity,hardware function library,memory modules,partitioning tool,program execution speed up,reconfigurable hardware,uniprocessor host | Computer science,Real-time computing,Software,Computer hardware,Application software,Uniprocessor system,Computer architecture,Hardware compatibility list,High-level synthesis,Field-programmable gate array,Hardware architecture,Reconfigurable computing,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-8186-8224-8 | 5 |
PageRank | References | Authors |
0.55 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. C. Jain | 1 | 11 | 2.89 |
| M. Balakrishnan | 2 | 518 | 72.63 |
| Anshul Kumar | 3 | 399 | 48.45 |
| Subodh Kumar | 4 | 527 | 49.65 |