Name
Abstract | ||
|---|---|---|
This paper describes a technique to accelerate diagnostic fault simulation of sequential circuits using fault sampling. Diagnostic fault simulation involves computing the indistinguishability relationship between all pairs of modeled faults. The input space is the set of all pairs of modeled faults, thus making the simulation computationally intensive. The diagnostic simulation process is accelerated by considering a sub-space of the input space that is obtained using fault sampling. Results on performance speedup and diagnostic resolution loss are provided for the ISCAS 89 benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICVD.1998.646652 | VLSI Design |
Keywords | Field | DocType |
fault diagnosis,logic testing,sequential circuits,diagnostic fault simulation,fault sampling,indistinguishability relationship,sequential circuit | Stuck-at fault,Sequential logic,Logic testing,Computer science,Systems analysis,Electronic engineering,Real-time computing,Sampling (statistics),Network analysis,Electronic circuit,Speedup | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-8186-8224-8 | 1 |
PageRank | References | Authors |
0.48 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Srikanth Venkataraman | 1 | 572 | 48.05 |
| W. K. Fuchs | 2 | 464 | 45.59 |
| J. H. Patel | 3 | 4577 | 527.59 |