| Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction | 20 | 0.96 | 2001 |
| Reversible Debugging Using Program Instrumentation | 16 | 0.97 | 2001 |
| Multiple design error diagnosis and correction in digital VLSI circuits | 11 | 0.80 | 1999 |
| Implication and evaluation techniques for proving fault equivalence | 11 | 0.83 | 1999 |
| PREACHES - Portable Recovery and Checkpointing in Heterogeneous Systems | 6 | 0.77 | 1998 |
| Diagnostic simulation of sequential circuits using fault sampling | 1 | 0.48 | 1998 |
| Partial scan design based on circuit state information | 23 | 1.06 | 1996 |
| Adaptive Recovery For Mobile Environments | 0 | 0.34 | 1996 |
| Compiler-based multiple instruction retry | 9 | 0.85 | 1995 |
| Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists | 42 | 2.39 | 1995 |
| Fault dictionary compression and equivalence class computation for sequential circuits | 54 | 4.17 | 1993 |
| Exact evaluation of diagnostic test resolution | 23 | 1.88 | 1992 |
| Site partitioning for distributed redundant disk arrays | 0 | 0.34 | 1992 |
| Branch recovery with compiler-assisted multiple instruction retry | 14 | 1.25 | 1992 |
| Diagnostic Fault Simulation of Sequential Circuits | 51 | 3.55 | 1992 |
| Compiler-assisted static checkpoint insertion | 27 | 3.37 | 1992 |
| Error Recovery in Shared Memory Multiprocessors Using Private Caches | 41 | 2.92 | 1990 |
| Forward Recovery Using Checkpointing in Parallel Systems | 16 | 2.15 | 1990 |
| Catch: compiler assisted techniques for checkpointing | 37 | 5.94 | 1990 |
| Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance | 44 | 5.33 | 1987 |
| An Efficient Approach to Gate Matrix Layout | 11 | 4.57 | 1987 |
| Concurrent error detection in VLSI interconnection networks | 7 | 0.67 | 1983 |
