Title
Joint Equalization and Coding for On-Chip Bus Communication
Abstract
In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.
Year
DOI
Venue
2005
10.1109/TVLSI.2007.915484
VLSI) Systems, IEEE Transactions
Keywords
Field
DocType
threshold inverter,on-chip buses,CMOS integrated circuits,word length 32 bit,delay,integrated circuit interconnections,isi,32 bit,rc limit,0.13-mum CMOS technology,size 10 mm,encoding,interconnect,equalization,crosstalk avoidance coding,interconnection networks,system-on-chip,crosstalk,10 mm,joint equalization-coding,rc delay,integrated circuit design,resistance-capacitance delay,variable threshold inverter,system-on-chip (SOC),switching threshold,on-chip bus communication,equalisers,interference suppression,invertors,Coding,equalizer,size 0.13 mum,network-on-chip,intersymbol interference,crosstalk avoidance,0.13 micron,ISI
Inverter,Intersymbol interference,System on a chip,Equalization (audio),Computer science,CMOS,Coding (social sciences),Electronic engineering,Integrated circuit design,RC time constant
Conference
Volume
Issue
ISSN
16
3
1063-8210
ISBN
Citations 
PageRank 
0-7695-2301-3
6
0.84
References 
Authors
9
3
Name
Order
Citations
PageRank
Srinivasa R. Sridhara11045.21
Naresh R. Shanbhag252150.27
Ganesh Balamurugan314420.77