Name
Abstract | ||
|---|---|---|
We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/VTEST.1998.670866 | Monterey, CA |
Keywords | Field | DocType |
circuit analysis computing,fault diagnosis,flip-flops,identification,integrated logic circuits,logic testing,redundancy,sequential circuits,sequential circuits,stuck-at fault,undetectable fault identification,undetectable fault removal,unreachable states | Stuck-at fault,Signal processing,Sequential logic,Computer science,Fault detection and isolation,Logic testing,Real-time computing,Combinational logic,Electronic engineering,Redundancy (engineering),Electronic circuit | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-8186-8436-4 | 6 |
PageRank | References | Authors |
1.00 | 6 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Kozo Kinoshita | 2 | 756 | 118.08 |