Name
Title | ||
|---|---|---|
Comments on "Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI" |
Year | DOI | Venue |
|---|---|---|
1986 | 10.1109/PROC.1986.13492 | Proceedings of the IEEE |
Keywords | DocType | Volume |
very large scale integration,logic circuits,probability,statistics,redundancy,predictive models | Journal | 74 |
Issue | ISSN | Citations |
3 | 0018-9219 | 26 |
PageRank | References | Authors |
5.24 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Harden, J.C. | 1 | 26 | 5.24 |
| Mangir, T.E. | 2 | 75 | 12.36 |