Paper Info
Title
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
Abstract
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (input CIMs) or between output of the logic cells and the global interconnect (output CIMs). It is demonstrated that an input CIM that connects Nin segments to a logic cell input requires Nin test configurations and that an output CIM that connects a logic cell output to Nout segments requires 2 test configurations. Then, it is proven that a set of Kin input CIMs can be tested in parallel making the number of required test configurations equal to N in. In the same way, a set of Kout output CIMs is shown to require only 2 test configurations if Nout>Kout. Finally, it is shown that the complete mXm array of logic cells with Kin input CIMs and K out output CIMs can be tested with only Nin test configurations using the XOR tree and shift register structures
Year
DOI
Venue
1999
10.1109/DATE.1999.761193
Munich
Keywords
Field
DocType
automatic testing,cellular arrays,field programmable gate arrays,integrated circuit interconnections,integrated circuit testing,logic testing,SRAM-based FPGAs,XOR tree,configurable interconnect/logic interface,global interconnect,input CIMs,logic cells,logic testing,output CIMs,shift register structures,test configurations
Logic gate,Shift register,Sequential logic,Pass transistor logic,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Static random-access memory,Logic family,Interconnection
Conference
ISBN
Citations 
PageRank 
0-7695-0078-1
10
0.76
References 
Authors
17
4
Name
Order
Citations
PageRank
M. Renovell122418.93
J. M. Portal217620.95
J. Figueras322719.91
Y. Zorian449947.97