Name
Abstract | ||
|---|---|---|
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the integrated circuit (IC) can be used for path delay fault testing of the IC. We show that the testing of the IC for path delay faults can be reduced to the testing of each block. Intellectual property (IP) blocks are treated as black boxes. The number of circuit paths that must be tested is almost equal to the sum of the paths that must be tested for each block |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/DATE.1999.761105 | Munich |
Keywords | Field | DocType |
VLSI,automatic testing,delays,fault diagnosis,industrial property,integrated circuit testing,logic testing,multiplexing equipment,circuit paths,embedded intellectual property blocks,logic testing,multiplexers,path delay fault testing,primary ports | Computer science,Automatic testing,Path delay,Real-time computing,Multiplexer,Industrial property,Black box,Intellectual property,Integrated circuit,Very-large-scale integration,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-0078-1 | 2 | 0.39 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Nikolos | 1 | 291 | 31.38 |
| Themistoklis Haniotakis | 2 | 97 | 16.09 |
| Haridimos T. Vergos | 3 | 64 | 8.11 |
| Y. Tsiatouhas | 4 | 68 | 11.07 |